A small engine.
A traceable system.
Training on the host. Binary inference on the chip. Verification between the two. Select a component to inspect its role, inputs, outputs and repository path.
The CDT
The command-line workflow orchestrates inspection, training, integer folding, export and validation. Training runs on the host, with optional accelerator support.
Model, data, TOML configuration
Trained binary model + generated C header
CDT → generated header → lib_symbex → hardware layer → device output. Verification compares that output to the host integer reference. Benchmarks use both the binary pipeline and an independent INT8 pipeline.Find the code
behind the concept.
The inference project stays separate from this website. Each component links directly to the inspected repository revision.
| Component | Responsibility | Source |
|---|---|---|
| The CDT | The command-line workflow orchestrates inspection, training, integer folding, export and validation. Training runs on the host, with optional accelerator support. | tools/cdt.py ↗ |
| lib_symbex | The portable C engine executes binary networks using counting and integer thresholds. Convolutional boolean networks use binary inputs and OR shortcuts. | Symbex1_PIO/lib/lib_symbex ↗ |
| Hardware layer | Generic, ESP32-S3 and RP2350 source modules provide chip-specific primitives; the generic module includes ESP32 and AVR paths. Hardware profiles guide selection of counting methods. | Symbex1_PIO/lib/lib_symbex/src/hal ↗ |
| Chip verification | The device runner flashes a board and checks its outputs against the PC simulation, then captures real-device measurements. | tools/chip_test.py ↗ |
| Benchmark suite | Task-specific studies compare the binary engine with independently produced TensorFlow Lite Micro INT8 baselines. Each workload documents its own conditions and limitations. | benchmarks ↗ |
One C engine.
A layer for the chip.
The HAL isolates the counting primitives that differ by target. The optimal method depends on the device and the size of the operation.
ESP32 / lookup tables and SWAR
Classic ESP32 lacks the S3’s 8-bit SIMD path. The project measures SWAR and table-based counting methods, including a 64 KB lookup table. Table storage is an additional resource cost.
ESP32-S3 / PIE SIMD
The S3 has SIMD multiplication but no popcount instruction. The engine uses measured chip-specific methods, including pie_swar, to count efficiently using the available arithmetic.
Generic C and AVR
The generic hardware module includes an AVR path using a small flash-resident lookup table. Inclusion is not a claim that all documented neural workloads have been benchmarked on every target.
Symbex1_PIO/
src/main.cpp # minimal board example
lib/lib_symbex/
include/ # public C interfaces
src/ # inference implementation
src/hal/ # target-specific primitives
tests/run_tests.py # bit-exact host tests
tools/
cdt.py # host-side workflow
chip_test.py # device runner
compiler_core/ # training/export machinery
benchmarks/ # independent comparisons