Seven stages. One traceable journey. Follow training, integer export and bit-exact verification, with the code behind every step.
Choose your model, data, and memory budget. For images, pixel channels become a thermometer of bits before the first binary layer.
[hardware] ram_kb = 320 flash_kb = 4096
ARTIFACT / symbex.toml
Choose your model, data, and memory budget. For images, pixel channels become a thermometer of bits before the first binary layer.
The CDT reads a TOML configuration. The boolean path uses the defined convolutional network; dense search can explore widths and precision within a hardware budget.
Inspect the source ↗Training happens on your computer. The network learns binary weights and activations, including its first convolutional layer.
The boolean path supports fully binary convolution, bitwise OR residual shortcuts and pooling. A validation split is used for model selection; test data should be evaluated once.
Inspect the source ↗Learned transformations fold into integer decision rules. A count and a threshold decide the next bit.
Scale, BatchNorm and activation are folded at export. XOR/AND conventions and threshold directions depend on the layer representation. The toy lab illustrates a count rule, not every runtime path.
Inspect the source ↗The exporter packs the trained network into a C header that the embedded inference engine can read.
Export emits binary weights, integer thresholds and network descriptors. The header is an interface to lib_symbex; it is not a standalone training runtime.
Inspect the source ↗The compiled C result is checked against the integer simulation on the PC. Every exported model must agree exactly.
Fidelity to the trained floating-point operations and exactness to the integer simulation are distinct checks. Bit-exactness describes implementation agreement, not dataset accuracy.
Inspect the source ↗The microcontroller runs the C engine. A hardware layer chooses how to count bits on the target chip.
ESP32 can use SWAR or a lookup table; ESP32-S3 uses its PIE SIMD arithmetic, including pie_swar. Training stays on the workstation.
Inspect the source ↗Compare device outputs with the PC reference, then inspect accuracy, latency and memory on real hardware.
The documented comparisons use one core at 240 MHz. Reported latency uses device timing and medians; seed statistics and baseline agreement are reported separately.
Inspect the source ↗Read at your own pace. The stage on the left follows the explanation, with no scroll hijacking.
Choose your model, data, and memory budget. For images, pixel channels become a thermometer of bits before the first binary layer.
The CDT reads a TOML configuration. The boolean path uses the defined convolutional network; dense search can explore widths and precision within a hardware budget.
Open source file ↗Training happens on your computer. The network learns binary weights and activations, including its first convolutional layer.
The boolean path supports fully binary convolution, bitwise OR residual shortcuts and pooling. A validation split is used for model selection; test data should be evaluated once.
Open source file ↗Learned transformations fold into integer decision rules. A count and a threshold decide the next bit.
Scale, BatchNorm and activation are folded at export. XOR/AND conventions and threshold directions depend on the layer representation. The toy lab illustrates a count rule, not every runtime path.
Open source file ↗The exporter packs the trained network into a C header that the embedded inference engine can read.
Export emits binary weights, integer thresholds and network descriptors. The header is an interface to lib_symbex; it is not a standalone training runtime.
Open source file ↗The compiled C result is checked against the integer simulation on the PC. Every exported model must agree exactly.
Fidelity to the trained floating-point operations and exactness to the integer simulation are distinct checks. Bit-exactness describes implementation agreement, not dataset accuracy.
Open source file ↗The microcontroller runs the C engine. A hardware layer chooses how to count bits on the target chip.
ESP32 can use SWAR or a lookup table; ESP32-S3 uses its PIE SIMD arithmetic, including pie_swar. Training stays on the workstation.
Open source file ↗Compare device outputs with the PC reference, then inspect accuracy, latency and memory on real hardware.
The documented comparisons use one core at 240 MHz. Reported latency uses device timing and medians; seed statistics and baseline agreement are reported separately.
Open source file ↗Try the count, threshold and encoding operations for yourself.